1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more specifically to a semiconductor integrated circuit which can reconcile a high speed operation in an active mode and a low power consumption in a standby mode.
2. Description of Related Art
Recently, a demand for a low power consumption is increasing around the field of a portable electronic information instrument, and to meet with this demand, a low power supply voltage for the LSI has been advanced. Here, in a circuit constituted of MOSFETs, if the power supply voltage expressed with VDD and a threshold of the MOSFET is expressed with VT, an operation speed of the circuit constituted of MOSFETs is in proportion to about (VDD-VT)2. As a result, if the power supply voltage is greatly lowered, the operation speed abruptly drops. In other words, in order to reconcile a high speed operation in an active condition and a low power consumption in a standby condition, it is extremely difficult to greatly lower the power supply voltage.
On the other hand, in order to elevate the operation speed, if the threshold voltage VT is lowered, a subthreshold current which flows through the MOSFET in an OFF condition, increases, with the result that the power consumption in the standby condition in which the LSI does not operate, greatly increases. For example, if the threshold voltage is lowered by 0.1V, the subthreshold current flowing through the MOSFET of the OFF condition increases more than ten times.
In the field of the portable electronic information instrument, it is a matter of course that the high speed operation is required, but the power consumption in the standby condition is a large factor which determines the lift of the battery cell. Therefore, particularly in a region of the power supply voltage not greater than 2V, it is an important technical problem to be solved that the high speed operation and the low power consumption are compatible.
In order to make the high speed operation and the low power consumption compatible to each other, for example, Japanese Patent Application Pre-examination Publication No. JP-A-06-029834 (U.S. Pat. No. 5,484,774, the content of which is incorporated by reference in its entirety into this application) discloses a technology of setting the active mode and the standby mode and stopping the supplying of the electric power in the standby mode, thereby to realize the lower power consumption.
In the technology disclosed by the above referred publication, MOSFETs having two kinds of threshold are used, and therefore, this is called a xe2x80x9cMulti-Threshold-CMOS technologyxe2x80x9d (abbreviated to xe2x80x9cMTCMOS technology, and called a first prior art).
Now, the first prior art will be described with reference to FIG. 11. In the shown example, logic circuits 11a and 11b are constituted of MOSFETs having a low threshold voltage, and have power terminals connected to quasi-power line QL1 and QL2, respectively. The quasi-power line QL1 and QL2 are connected through power switches 101 and 102 to power supply lines PL1 and PL2, respectively.
The power switches 101 and 102 are MOSFETs having a high threshold voltage, and supplied with control signals CS and CSB so as to be turned on in the active mode and off in the standby mode. If the size of the power switches 101 and 102 is set to be sufficiently large, the potentials of the quasi-power line QL1 and QL2 can be made substantially equal to those of the power supply lines PL1 and PL2, respectively, in the active mode. As a result, the operation speed of the low threshold logic circuit is not almost deteriorated. In the standby mode, the power switches 101 and 102 are turned off, so that the supplying of the power is stopped, with the result that the low power consumption can be realized although the logic circuit is constituted of the low threshold MOSFETs.
Furthermore, the shown example includes an information hold circuit 11c, which is constituted of for example a latch circuit, which holds information in the standby mode. In this information hold circuit 11c, both of the high threshold MOSFETs and the low threshold MOSFETs are used. The low threshold MOSFETs are used in a circuit of determining the operation speed in the action condition, and power terminals of that circuit are connected to the quasi-power line QL1 and QL2, respectively. The high threshold MOSFETs are used in a circuit of holding the information in the standby condition, and power terminals of that circuit are connected to the power supply lines PL1 and PL2, respectively. With this arrangement, the power is supplied even in the standby mode, so that the information is held, and on the other hand, the low power consumption is realized.
In this MTCMOS technology, however, the design of the circuit for holding the information in the standby mode, is very important. Here, the latch circuit will be described as an example. FIG. 12 is one example of the latch circuit used in the prior art (not the MTCMOS technology). The shown latch circuit includes complementary pass transistors 103 and 104 having respective gate terminals receiving a pair of complementary clocks CK and CKB. Furthermore, the latch circuit includes inverter circuits 105 and 106, which are connected to power supply lines VCC and VSS, respectively. In this latch circuit, an input data is fetched by turning on the path transistors 103 and by turning off the path transistors 104, and the information is held by turning off the path transistors 103 and by turning on the path transistors 104.
FIG. 13 is one example of applying the latch circuit shown in FIG. 12 to the MTCMOS technology. The shown latch circuit includes complementary path transistors 111 and 112 having respective gate terminals receiving a pair of complementary clocks CK and CKB. A pair of power supply terminals of an inverter circuit 113 are connected through power switches 116 and 117 to the power supply lines PL1 and PL2, respectively. Gate terminals of these power switches 116 and 117 are supplied with the control signals CS and CSB, respectively, so that the power switches 116 and 117 are turned on in the active mode and are turned off in the standby mode. A pair of power supply terminals of inverter circuit 114 and 115 are connected to the power supply lines PL1 and PL2, respectively.
The path transistors 111 and the inverter circuit 113 are constituted of the low threshold MOSFETs, and the inverter circuits 114 and 115 and the power switches 116 and 117 are constituted of the high threshold MOSFETs. Incidentally, the path transistors 112 can be constituted of either the low threshold MOSFETs or the high threshold MOSFETs, and the data fetching operation and the data holding operation are similar to those of the prior art latch circuit shown in FIG. 12.
As mentioned above, since the path transistors 111 and the inverter circuit 113 are constituted of the low threshold MOSFETs, the high speed operation can be realized. In the standby mode, the path transistors 111 are turned off and the path transistors 112 are turned on so that the information is held in a loop composed of the path transistors 112 and the inverter circuits 114 and 115. As mentioned above, since the inverter circuits 114 and 115 are constituted of the high threshold MOSFETs, the low power consumption can be realized.
However, this latch circuit has a problem in which the power switches cannot be used in common to other circuits. Even in the standby mode, an input potential and an output potential of the inverter circuit 113 are fixed by the inverter circuits 114 and 115. Therefore, when the input potential is at a low level, an internal node 118 is connected to the power supply line PL1 through a PMOS transistor of the inverter circuit 113 and a PMOS transistor of the inverter circuit 115 with a low impedance. When the input potential is at a high level, an internal node 119 is connected to the power supply line PL2 through an NMOS transistor of the inverter circuit 113 and an NMOS transistor of the inverter circuit 115. Therefore, if the internal nodes 118 and 119 of the latch circuit are made as the quasi-power lines QL1 and QL2 in common to other circuits, the electric power is supplied to the circuit constituted of the low threshold MOSFETs in the standby mode, with the result that the power consumption becomes increased.
Because of this, the power switches must be provided for each latch circuit. However, since the power switches cannot be made large because of the restriction of the area, the operation speed of the latch circuit becomes slow.
In order to overcome the above mentioned problem, the technology called a xe2x80x9cballoonxe2x80x9d is proposed by SHIGEMATSU et al in 1995 Symposium on VLSI Circuits Digest, pp.125-126 (this will be called a second prior art). FIG. 14 is an example of applying this balloon technology to the prior art latch shown in FIG. 12. The latch circuit shown in FIG. 14 is the prior art latch circuit connected with a memory cell. In the drawing, a left side circuit part is the prior art latch circuit added with complementary path transistors 125. In this part, all the path transistors are formed of the low threshold MOSFETs. Power terminals of this part are connected to the quasi-power lines QL1 and QL2, respectively. The memory cell is constituted of complementary path transistors 126 and 127 and inverter circuits 128 and 129, and is connected to an internal node 130 of the latch circuit.
The path transistors 127 are constituted of the low threshold MOSFETs, and the path transistors 126 and the inverter circuits 128 and 129 are constituted of the high threshold MOSFETs. Power terminals of the inverter circuits 128 and 129 are connected to the power supply lines PL1 and PL2, respectively.
Control signals B2 and B2B are supplied to the effect that in the active mode, the path transistors 125 are turned on, and the path transistors 127 are turned off, and in the standby mode, these conditions are inverted. When it becomes the standby mode and when it returns to the active mode, control signals B1 and B1B are supplied to turn on the path transistors 126, so that the internal node 130 of the latch circuit is connected to the memory cell. Thus, information to be held is written into the memory cell before it enters the standby mode, and the information is read out from the memory cell before it returns to the active mode.
In the standby mode, the memory cell is separated from the latch circuit, and internal nodes other than the memory cell can be put in a floating condition. Therefore, the quasi-power lines QL1 and QL2 can be used in common to the other circuits. Accordingly, since the power switches can be made in common to the other circuits and can be enlarged in size, the high speed operation can be realized.
Another technology of setting the active mode and the standby mode and of stopping the supplying of the electric power in the standby mode, similarly to the above prior art, is proposed by for example Japanese Patent Application Pre-examination Publication No. JP-A-05-291929 (corresponding, in part, to U.S. Pat. No. 5,583,457, the content of which is incorporated by reference in its entirety into this application) (this will be called a third prior art).
FIG. 15 is an example of applying the third prior art to an inverter circuit. A PMOS transistor 131 and an NMOS transistor 132 are the low threshold MOSFETs, and constitute an inverter circuit INV. One power supply terminal of the inverter circuit is connected to a high level power supply line VHH, and the other power supply terminal of the inverter circuit is connected to a low level power supply line VLL. A PMOS transistor 133 and an NMOS transistor 134 are the high threshold MOSFETs, and operate as a power switch. Control signals SWU and SWL are supplied to gate terminals of these transistors so that the power switches are turned off in the standby mode. A level hold circuit is constituted of inverter circuits 135 and 136, and constituted of the high threshold MOSFETs. Power supply terminals of the level hold circuit are connected directly to the power supply lines VHH and VLL.
In the standby mode, necessary information is held in the level hold circuit. In the third prior art, no latch circuit is described, but when the third prior art is used with the latch circuit, for example the latch circuit shown in FIG. 12 is inserted into a portion of the inverter circuit INV in FIG. 15.
As mentioned hereinbefore, the latch circuit of the first prior art has a problem in which, since the power switches must be provided for each one latch circuit, the power switches cannot be very enlarged, so that the operation speed is slow. There is another problem in which the power switch for the logic circuit must be inserted to both a high level power supply line side and a low level power supply line side. This is because the complementary path transistors 111 of the latch circuit shown in FIG. 13 are constituted of the low threshold MOSFETs. In the standby mode, the complementary path transistors 111 are in the OFF condition, there is possibility that the subthreshold current flows through a preceding stage circuit. In order to prevent this problem, in the preceding stage logic circuit, the power switch must be inserted to both a high level power supply line side and a low level power supply line side. Of course, if the complementary path transistors 111 are constituted of the high threshold MOSFETs, it becomes sufficient if the power switch is inserted to only one side, but with this arrangement, the operation speed of the latch circuit becomes very slow.
The latch circuit of the second prior art can overcome the problem in the latch circuit of the first prior art, but has another problem in which the control signals are many, and therefore, a fine timing control is required in the operation for changing over the mode.
The third prior art has a problem in which the power switch for the logic circuit must be inserted to both a high level power supply line side and a low level power supply line side, similarly to the first prior art.
Accordingly, it is an object of the present invention to provide a semiconductor integrated circuit which can reconcile a high speed operation in an active mode and a low power consumption in a standby mode.
Another object of the present invention is to provide such a semiconductor integrated circuit with a reduced number of required control signals, without requiring the fine timing control for changing over the mode, and with the power switch which is provided for the low threshold logic circuit and which is sufficient if it is inserted to only either of a high level power supply line side and a low level power supply line side.
The latch circuit used in the semiconductor integrated circuit in accordance with the present invention having the active mode and the standby mode, is characterized in that a high threshold first conductivity type MOSFET and a low threshold second conductivity type MOSFET are used as MOSFETs applied with a control signal, and a voltage amplitude of the control signal is larger than a power supply voltage It is also characterized in that, as the control signal, a clock signal is supplied in the active mode, and a signal for creating an information hold condition is supplied in the standby mode.
In order to achieve the high speed operation in the active mode, it is necessary to elevate an effective gate voltage (VGS-VT) of the MOSFET in the ON condition. Here, VGS is a voltage between a gate terminal and a source terminal of the MOSFET. On the other hand, in order to achieve the low power consumption in the standby mode, it is necessary to lower the effective gate voltage (VGS-VT) of the MOSFET in the OFF condition. In the first conductivity type MOSFET, the former can be realized by a high VGS, and the latter can be realized by a high VT. In the second conductivity type MOSFET, the former can be realized by a low VGS, and the latter can be realized by a low VT. With this arrangement, the high speed operation in the active mode and the low power consumption in the standby mode can be made compatible with each other. In addition, in the standby mode, since complementary path transistors at an input of the latch circuit can be put in a completely OFF condition, the latch circuit can be isolated from a preceding stage, and therefore, it is sufficient if the power switch for the low threshold logic circuit is inserted to only either of the high level power supply voltage side and the low level power supply voltage side.
In addition, if, as the control signal, the clock signal is supplied in the active mode, and the signal for creating the information hold condition is supplied in the standby mode, the power switch for the latch circuit can be caused to have a function of the complementary path transistors. Therefore, since the latch circuit is completely isolated from the preceding stage by a gate oxide film of the MOSFET, it is sufficient if the power switch for the low threshold logic circuit is inserted to only either of the high level power supply voltage side and the low level power supply voltage side.